(1) Field of the Invention
This invention relates to the formation of a low cost integrated resistor capacitor combination and more specifically to the use of anodization to form a capacitor dielectric thereby reducing the number of mask steps required.
(2) Description of the Related Art
U.S. Pat. No. 4,781,802 to Fresia describes the anodization of porous tantalum pellets under various anodization and heat treatment conditions to improve the dielectric oxide.
U.S. Pat. No. 5,541,442 to Keil et al. describes a capacitor configuration using FET technology. The diffusion zone of the substrate is used as one plate of the capacitor and the gate electrode of an FET is the other plate the two plates being separated by a conventional thin dielectric gate oxide layer.
U.S. Pat. No. 5,422,293 to Konya shows a method for forming resistors and capacitors. Oxide films are formed on the surfaces of the gate line and the capacitor lines by anodization to prevent shorting of these lines.
U.S. Pat. No. 5,583,068 to Jones, Jr. et al. describes a method of forming a capacitor with a metal-oxide dielectric layer.
U.S. Pat. No. 4,251,326 to Arcidiacono et al. and U.S. Pat. No. 4,410,867 to Arcidiacono et al. describe a method of forming a thin film resistor capacitor network. A film of alpha titanium is deposited and anodized to form bottom capacitor plates and a capacitor dielectric. A film of titanium nitride is later deposited to form resistors.
The present invention describes a method of forming an integrated resistor capacitor combination using a layer of resistor material patterned to form resistors and first capacitor plates. A capacitor dielectric is then formed on the first capacitor plates using anodization. An overlaying conductor layer is then patterned to form resistor contacts, contacts to the first capacitor plates, and second capacitor plates.